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Principal Digital Verification Engineer

Req ID: J2368321-IL

  • Location
    Remote - USA
  • Category Design Services Group
  • Posted Friday, July 28, 2023
  • Type Full time
  • Job Type Permanent Employee

At Jabil we strive to make ANYTHING POSSIBLE and EVERYTHING BETTER. With over 250,000 diverse, talented and dedicated employees across 100 locations in 30 countries, our vision is to be the most technologically advanced and trusted manufacturing solutions provider. We combine an unmatched breadth and depth of end-market experience, technical and design capabilities, manufacturing know-how, supply chain insights and global product management expertise to enable success for the world’s leading brands. We are driven by a common purpose to make a positive impact for each other, our communities, and the environment.

Job Description


As a Principal Digital Verification Engineer you will have developed an expertise in a particular field of engineering or within a particular sector. You will have lead design teams through full product development and into production. As a Principal, you will be expected to demonstrate a level of expertise in a particular area that matches or exceeds the expertise of our customers. You will consult on system architectures, assess technical requirements and competencies needed during quoting and oversee design progressions during product developments.



  • FPGA and Digital Design Expertise: A strong background in FPGA and digital design is essential. This includes a deep understanding of FPGA architectures, digital circuits, and RTL (Register Transfer Level) design.
  • Verification Methodology: Expertise in verification methodologies, with a focus on uVM. Experience in developing and implementing uVM-based testbenches to verify FPGA designs.
  • SystemVerilog and RTL Languages: Proficiency in hardware description languages like SystemVerilog is crucial, as uVM is built on top of SystemVerilog. A principal FPGA verification engineer should be comfortable with writing and analyzing RTL code.
  • Verification Tools: Familiarity with industry-standard FPGA verification tools, such as ModelSim, Questa, or VCS. These tools are used to simulate and debug the uVM-based testbenches.
  • FPGA Development Tools: Experience with FPGA development tools from vendors like Xilinx or Intel (formerly Altera). Knowledge of FPGA synthesis, place-and-route, and timing analysis is beneficial.
  • Test Plan Development: Ability to create detailed test plans based on design specifications and requirements. This involves defining test cases and functional coverage goals.
  • Verification IP (VIP): Knowledge of Verification IP usage in uVM testbenches. VIPs are pre-built verification components that help accelerate the verification process.
  • Matlab Model Integration: The ability to integrate Matlab models into the FPGA verification environment.
  • Debugging Skills: Strong problem-solving and debugging capabilities are essential to identify and resolve issues in the FPGA design and testbench.
  • Scripting Languages: Proficiency in scripting languages like Perl, Python, or TCL can be valuable for automation and productivity improvement.
  • Communication and Leadership: As a principal engineer, the ability to effectively communicate with cross-functional teams, mentor junior engineers, and provide technical leadership is vital.
  • Industry Standards:  3GPP standards LTE/5G, ORAN  Standard, Ethernet protocol
  • Test Automation: Experience in automating the verification process using scripts and testbenches. Automation helps speed up the verification process and allows for regression testing
  • ORAN Standard Knowledge: Familiarity with the ORAN standard
  • 3GPP Wireless Standards: Familiarity with 3GPP wireless standards (e.g., LTE, 5G NR)
  • Digital Signal Processing (DSP): Knowledge of digital signal processing concepts and algorithms is valuable
  • Able to work closely with digital designers, Test engineers, Software developers, and manufacturing test to support Radio Head testing
  • Knowledge of signal processing and System Verilog Assertions

Ability to read, analyze, and interpret general business periodicals, professional journals, technical procedures, or governmental regulations. Ability to write reports, business correspondence, and procedure manuals. Ability to effectively present information and respond to questions from groups of managers, clients, customers, and the general public.

Ability to work with mathematical concepts such as probability and statistics, and fundamentals of plane and solid geometry and trigonometry. Ability to apply concepts such as fractions, percentages, ratios, and proportions to practical situations.

Ability to define problems, collect data, establish facts, and draw valid conclusions. Ability to interpret an extensive variety of technical instructions in mathematical or diagram form and deal with several abstract and concrete variables. Ability to develop mathematical models of physical reality and solve them, then implement the results.


·         Masters degree in Engineering from an accredited four-year college or university
·         Minimum of 11-12 years of related experience and/or training
·         Minimum of 2 years experience as a Lead Engineer
·         Specific requirements as defined by the market sector
·         Or an equivalent combination of education, training or experience.

Jabil, including its subsidiaries, is an equal opportunity employer and considers qualified applicants for employment without regard to race, color, religion, national origin, sex, sexual orientation, gender identify, age, disability, genetic information, veteran status, or any other characteristic protected by law.

BE AWARE OF FRAUD: When applying for a job at Jabil you will be contacted via correspondence through our official job portal with a e-mail address; direct phone call from a member of the Jabil team; or direct e-mail with a e-mail address. Jabil does not request payments for interviews or at any other point during the hiring process. Jabil will not ask for your personal identifying information such as a social security number, birth certificate, financial institution, driver’s license number or passport information over the phone or via e-mail. If you believe you are a victim of identity theft, contact the Federal Bureau of Investigations internet crime hotline (, the Federal Trade Commission identity theft hotline ( and/or your local police department. Any scam job listings should be reported to whatever website it was posted in.

The pay range for this role is $116,421 - $209,557. Job-related, non-discriminatory factors used to determine the actual offered rate include qualifications and experience, geographic location, education, external market data, and consideration of internal equity.

As part of the total rewards package, this position is eligible for a short-term incentive based on performance. In addition, Jabil offers benefits to enhance your health, wealth, and resilient self. These include medical, dental, and vision insurance plans; paid time off accruing at a rate of 3.07 hours during your first year of employment; 4 weeks of paid parental leave; in 2023, 10 company-paid holidays (8 fixed holidays and 2 optional floating holidays), subject to change yearly; 401(k) retirement plan; and employee stock purchase plan.

Accessibility Accommodation

If you are a qualified individual with a disability, you have the right to request a reasonable accommodation if you are unable or limited in your ability to use or access site as a result of your disability. You can request a reasonable accommodation by sending an e-mail to with the nature of your request and contact information. Please do not direct any other general employment related questions to this e-mail. Please note that only those inquiries concerning a request for reasonable accommodation will be responded to from this e-mail address.

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